CpuId

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Results with Julia v1.2.0

Testing was successful. Last evaluation was ago and took 49 seconds.

Click here to download the log file.

 Resolving package versions...
 Installed CpuId ─ v0.2.2
  Updating `~/.julia/environments/v1.2/Project.toml`
  [adafc99b] + CpuId v0.2.2
  Updating `~/.julia/environments/v1.2/Manifest.toml`
  [adafc99b] + CpuId v0.2.2
  [2a0f44e3] + Base64 
  [8ba89e20] + Distributed 
  [b77e0a4c] + InteractiveUtils 
  [56ddb016] + Logging 
  [d6f4376e] + Markdown 
  [9a3f8284] + Random 
  [9e88b42a] + Serialization 
  [6462fe0b] + Sockets 
  [8dfed614] + Test 
   Testing CpuId
    Status `/tmp/jl_yC2IGq/Manifest.toml`
  [adafc99b] CpuId v0.2.2
  [2a0f44e3] Base64  [`@stdlib/Base64`]
  [8ba89e20] Distributed  [`@stdlib/Distributed`]
  [b77e0a4c] InteractiveUtils  [`@stdlib/InteractiveUtils`]
  [56ddb016] Logging  [`@stdlib/Logging`]
  [d6f4376e] Markdown  [`@stdlib/Markdown`]
  [9a3f8284] Random  [`@stdlib/Random`]
  [9e88b42a] Serialization  [`@stdlib/Serialization`]
  [6462fe0b] Sockets  [`@stdlib/Sockets`]
  [8dfed614] Test  [`@stdlib/Test`]
| Cpu Property       | Value                                                      |
|:------------------ |:---------------------------------------------------------- |
| Brand              | Intel(R) Xeon(R) Silver 4114 CPU @ 2.20GHz                 |
| Vendor             | :Intel                                                     |
| Architecture       | :Skylake                                                   |
| Model              | Family: 0x06, Model: 0x55, Stepping: 0x04, Type: 0x00      |
| Cores              | 10 physical cores, 20 logical cores (on executing CPU)     |
|                    | Hyperthreading detected                                    |
| Clock Frequencies  | 2200 / 3000 MHz (base/max), 100 MHz bus                    |
| Data Cache         | Level 1:3 : (32, 1024, 14080) kbytes                       |
|                    | 64 byte cache line size                                    |
| Address Size       | 48 bits virtual, 46 bits physical                          |
| SIMD               | 512 bit = 64 byte max. SIMD vector size                    |
| Time Stamp Counter | TSC is accessible via `rdtsc`                              |
|                    | TSC runs at constant rate (invariant from clock frequency) |
| Perf. Monitoring   | Performance Monitoring Counters (PMC) revision 4           |
|                    | Available hardware counters per logical core:              |
|                    | 3 fixed-function counters of 48 bit width                  |
|                    | 4 general-purpose counters of 48 bit width                 |
| Hypervisor         | No                                                         |

| Cpu Feature | Description                                                    |
|:----------- |:-------------------------------------------------------------- |
| ACPI        | Thermal monitor and software controlled clock facilities (MSR) |
| ADX         | Intel ADX (Multi-Precision Add-Carry Instruction Extensions)   |
| AES         | AES encryption instruction set                                 |
| AHF64       | LAHF and SAHF in PM64                                          |
| APIC        | APIC on-chip (Advanced Programmable Interrupt Controller)      |
| AVX         | 256bit Advanced Vector Extensions, AVX                         |
| AVX2        | SIMD 256bit Advanced Vector Extensions 2                       |
| AVX512BW    | AVX-512 Byte and Word Instructions                             |
| AVX512CD    | AVX-512 Conflict Detection Instructions                        |
| AVX512DQ    | AVX-512 Doubleword and Quadword Instructions                   |
| AVX512F     | AVX-512 Foundation                                             |
| AVX512VL    | AVX-512 Vector Length Extensions                               |
| BMI1        | Bit Manipulation Instruction Set 1                             |
| BMI2        | Bit Manipulation Instruction Set 2                             |
| CLFLUSH     | CLFLUSHOPT Instructions                                        |
| CLFSH       | CLFLUSH instruction (SSE2)                                     |
| CLWB        | CLWB instruction                                               |
| CMOV        | Conditional move CMOV and FCMOV instructions                   |
| CX16        | CMPXCHG16B instruction                                         |
| CX8         | CMPXCHG8 instruction (64bit compare and exchange)              |
| DCA         | Direct cache access for DMA writes                             |
| DE          | Debugging extensions                                           |
| DS          | Debug store to save trace of executed jumps                    |
| DSCPL       | CPL qualified debug store                                      |
| DTES64      | 64bit debug store                                              |
| ERMS        | Enhanced REP MOVSB/STOSB                                       |
| EST         | Enhanced SpeedStep                                             |
| F16C        | half-precision float support                                   |
| FMA3        | Fused multiply-add using three operands                        |
| FPDPR       | FPU CS and FPU DS deprecated                                   |
| FPU         | Onboard x87 FPU                                                |
| FSGS        | Access to base of %fs and %gs                                  |
| FXSR        | FXSAVE, FXRSTOR instructions                                   |
| HLE         | Transactional Synchronization Extensions                       |
| HTT         | Max APIC IDs reserved field is valid                           |
| INVPCID     | INVPCID instruction                                            |
| IPT         | Intel Processor Trace                                          |
| LM          | AMD64 long mode                                                |
| LZCNT       | LZCNT instruction                                              |
| MCA         | Machine Check Architecture (MSR)                               |
| MCE         | Machine check exception                                        |
| MMX         | 64bit Multimedia Streaming Extensions                          |
| MON         | MONITOR and MWAIT instructions                                 |
| MOVBE       | MOVBE instruction                                              |
| MPX         | Intel MPX (Memory Protection Extensions)                       |
| MSR         | Model Specific Registers, RDMSR and WRMSR instructions         |
| MTRR        | Memory Type Range Registers                                    |
| NX          | NXE                                                            |
| OSPKE       | PKU enabled by OS                                              |
| OSXSV       | XSAVE enabled by OS                                            |
| PAE         | Physical address extension                                     |
| PAT         | Page attribute table                                           |
| PBE         | Pending break enable wakeup support                            |
| PCID        | Process context identifiers                                    |
| PCLMUL      | PCLMULQDQ support                                              |
| PDCM        | Perfmon and debug capabilities                                 |
| PG1G        | PG1G                                                           |
| PGE         | Page global bit                                                |
| PKU         | Memory Protection Keys for User-mode pages                     |
| POPCNT      | POPCNT instruction                                             |
| PQE         | Platform Quality of Service Enforcement                        |
| PQM         | Platform Quality of Service Monitoring                         |
| PREFETCHW   | PREFETCHW instruction                                          |
| PSE         | Page size extensions                                           |
| PSE36       | 36bit page size extension                                      |
| RDRND       | On-chip random number generator                                |
| RDSEED      | RDSEED instruction                                             |
| RDTSCP      | RDTSCP instruction                                             |
| RTM         | Transactional Synchronization Extensions                       |
| SDBG        | Silicon debug interface                                        |
| SEP         | SYSENTER and SYSEXIT instructions                              |
| SMAP        | Supervisor Mode Access Prevention                              |
| SMEP        | Supervisor-Mode Execution Prevention                           |
| SMX         | Safer mode instructions                                        |
| SS          | Self Snoop                                                     |
| SSE         | 128bit Streaming SIMD Extensions 1                             |
| SSE2        | 128bit Streaming SIMD Extensions 2                             |
| SSE3        | 128bit Streaming SIMD Extensions 3                             |
| SSE41       | 128bit Streaming SIMD Extensions 4.1                           |
| SSE42       | 128bit Streaming SIMD Extensions 4.2                           |
| SSSE3       | 128bit Supplemental Streaming SIMD Extension 3                 |
| SYSCALL     | SYSCALL and SYSRET                                             |
| TM          | Thermal monitor with automatic thermal control                 |
| TM2         | Thermal monitor 2                                              |
| TSC         | Time stamp counter                                             |
| TSCADJ      | IA32_TSC_ADJUST                                                |
| TSCDL       | APIC one-shot operation using TSC deadline value               |
| TSCINV      | Invariant TSC                                                  |
| VME         | Virtual 8086 mode enhancements                                 |
| VMX         | Virtual machine extensions                                     |
| X2APIC      | x2APIC support                                                 |
| XSAVE       | XSAVE, XRESTOR, XSETBV, XGETBV                                 |
| XTPR        | disabling sending of task priority messages                    |



processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 85
model name	: Intel(R) Xeon(R) Silver 4114 CPU @ 2.20GHz
stepping	: 4
microcode	: 0x200005e
cpu MHz		: 2385.231
cache size	: 14080 KB
physical id	: 0
siblings	: 20
core id		: 0
cpu cores	: 10
apicid		: 0
initial apicid	: 0
fpu		: yes
fpu_exception	: yes
cpuid level	: 22
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cdp_l3 invpcid_single pti intel_ppin ssbd mba ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm mpx rdt_a avx512f avx512dq rdseed adx smap clflushopt clwb intel_pt avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req pku ospke md_clear flush_l1d
bugs		: cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass l1tf mds swapgs
bogomips	: 4400.00
clflush size	: 64
cache_alignment	: 64
address sizes	: 46 bits physical, 48 bits virtual
power management:
Test Summary: | Pass  Total
ReturnTypes   |   49     49
Dump of all cpuid leafs, used for mocking 'cpuid'...

# Intel(R) Xeon(R) Silver 4114 CPU @ 2.20GHz without hypervisor
push!( _mockdb, (Dict(
    ((0x00000000, 0x00000000) => (0x00000016, 0x756e6547, 0x6c65746e, 0x49656e69)),
    ((0x00000001, 0x00000000) => (0x00050654, 0x14200800, 0x7ffefbff, 0xbfebfbff)),
    ((0x00000002, 0x00000000) => (0x76036301, 0x00f0b5ff, 0x00000000, 0x00c30000)),
    ((0x00000003, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000004, 0x00000000) => (0x3c004121, 0x01c0003f, 0x0000003f, 0x00000000)),
    ((0x00000005, 0x00000000) => (0x00000040, 0x00000040, 0x00000003, 0x00002020)),
    ((0x00000006, 0x00000000) => (0x00000ef7, 0x00000002, 0x00000009, 0x00000000)),
    ((0x00000007, 0x00000000) => (0x00000000, 0xd39ffffb, 0x00000018, 0x9c002400)),
    ((0x00000008, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000009, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x0000000a, 0x00000000) => (0x07300404, 0x00000000, 0x00000000, 0x00000603)),
    ((0x0000000b, 0x00000000) => (0x00000001, 0x00000002, 0x00000100, 0x00000014)),
    ((0x0000000c, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x0000000d, 0x00000000) => (0x000002ff, 0x00000a88, 0x00000a88, 0x00000000)),
    ((0x0000000e, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x0000000f, 0x00000000) => (0x00000000, 0x0000004f, 0x00000000, 0x00000002)),
    ((0x00000010, 0x00000000) => (0x00000000, 0x0000000a, 0x00000000, 0x00000000)),
    ((0x00000011, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000012, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000013, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000014, 0x00000000) => (0x00000001, 0x0000000f, 0x00000007, 0x00000000)),
    ((0x00000015, 0x00000000) => (0x00000002, 0x000000b0, 0x00000000, 0x00000000)),
    ((0x00000016, 0x00000000) => (0x00000898, 0x00000bb8, 0x00000064, 0x00000000)),
    ((0x80000000, 0x00000000) => (0x80000008, 0x00000000, 0x00000000, 0x00000000)),
    ((0x80000001, 0x00000000) => (0x00000000, 0x00000000, 0x00000121, 0x2c100800)),
    ((0x80000002, 0x00000000) => (0x65746e49, 0x2952286c, 0x6f655820, 0x2952286e)),
    ((0x80000003, 0x00000000) => (0x6c695320, 0x20726576, 0x34313134, 0x55504320)),
    ((0x80000004, 0x00000000) => (0x32204020, 0x4730322e, 0x00007a48, 0x00000000)),
    ((0x80000005, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x80000006, 0x00000000) => (0x00000000, 0x00000000, 0x01006040, 0x00000000)),
    ((0x80000007, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000100)),
    ((0x80000008, 0x00000000) => (0x0000302e, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000004, 0x00000001) => (0x3c004122, 0x01c0003f, 0x0000003f, 0x00000000)),
    ((0x00000004, 0x00000002) => (0x3c004143, 0x03c0003f, 0x000003ff, 0x00000000)),
    ((0x00000004, 0x00000003) => (0x3c07c163, 0x0280003f, 0x00004fff, 0x00000004)),
    ((0x00000004, 0x00000004) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x0000000b, 0x00000001) => (0x00000005, 0x00000014, 0x00000201, 0x00000014)),
    ((0x0000000b, 0x00000002) => (0x00000000, 0x00000000, 0x00000002, 0x00000014)),
  ) => Dict{Symbol,Any}(
    :cpuvendor       => :Intel,
    :cpuarchitecture => :Skylake,
    :cpucores        => 10,
    :cputhreads      => 20,
    :cachesize       => (32768, 1048576, 14417920),
    :cachelinesize   => 64,
    :simdbits        => 512,
  )))

Done.



-----
Mocking CpuId
-----

Tested recorded cpuid table #1 for ''
Tested recorded cpuid table #2 for 'Intel(R) Xeon(R) CPU E5-2670 0 @ 2.60GHz'
Tested recorded cpuid table #3 for 'Intel(R) Xeon(R) CPU E5-2680 v2 @ 2.80GHz'
Tested recorded cpuid table #4 for 'Intel(R) Xeon(R) CPU E5-2680 v3 @ 2.50GHz'
Tested recorded cpuid table #5 for 'Intel(R) Xeon(R) CPU E5-2670 0 @ 2.60GHz'
Tested recorded cpuid table #6 for 'Intel(R) Xeon(R) CPU           X5570  @ 2.93GHz'
Tested recorded cpuid table #7 for 'Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz'
Tested recorded cpuid table #8 for 'Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz'
Tested recorded cpuid table #9 for 'Intel(R) Xeon Phi(TM) CPU 7250 @ 1.40GHz'
Tested recorded cpuid table #10 for 'Intel(R) Xeon(R) CPU E3-1241 v3 @ 3.50GHz'
Tested recorded cpuid table #11 for 'Intel(R) Core(TM) i7-6600U CPU @ 2.60GHz'
Tested recorded cpuid table #12 for 'AMD A10-8700P Radeon R6, 10 Compute Cores 4C+6G'
Tested recorded cpuid table #13 for 'AMD Ryzen Threadripper 1950X 16-Core Processor'
Tested recorded cpuid table #14 for 'AMD A8-6410 APU with AMD Radeon R5 Graphics'
Tested recorded cpuid table #15 for 'AMD Athlon(tm) 5350 APU with Radeon(tm) R3'
Tested recorded cpuid table #16 for 'AMD EPYC 7401P 24-Core Processor'
Test Summary: | Pass  Broken  Total
Mocking       |  174       2    176
   Testing CpuId tests passed 

Results with Julia v1.3.0

Testing was successful. Last evaluation was ago and took 1 minute, 4 seconds.

Click here to download the log file.

 Resolving package versions...
 Installed CpuId ─ v0.2.2
  Updating `~/.julia/environments/v1.3/Project.toml`
  [adafc99b] + CpuId v0.2.2
  Updating `~/.julia/environments/v1.3/Manifest.toml`
  [adafc99b] + CpuId v0.2.2
  [2a0f44e3] + Base64 
  [8ba89e20] + Distributed 
  [b77e0a4c] + InteractiveUtils 
  [56ddb016] + Logging 
  [d6f4376e] + Markdown 
  [9a3f8284] + Random 
  [9e88b42a] + Serialization 
  [6462fe0b] + Sockets 
  [8dfed614] + Test 
   Testing CpuId
    Status `/tmp/jl_PaVznI/Manifest.toml`
  [adafc99b] CpuId v0.2.2
  [2a0f44e3] Base64  [`@stdlib/Base64`]
  [8ba89e20] Distributed  [`@stdlib/Distributed`]
  [b77e0a4c] InteractiveUtils  [`@stdlib/InteractiveUtils`]
  [56ddb016] Logging  [`@stdlib/Logging`]
  [d6f4376e] Markdown  [`@stdlib/Markdown`]
  [9a3f8284] Random  [`@stdlib/Random`]
  [9e88b42a] Serialization  [`@stdlib/Serialization`]
  [6462fe0b] Sockets  [`@stdlib/Sockets`]
  [8dfed614] Test  [`@stdlib/Test`]
| Cpu Property       | Value                                                      |
|:------------------ |:---------------------------------------------------------- |
| Brand              | Intel(R) Xeon(R) Silver 4114 CPU @ 2.20GHz                 |
| Vendor             | :Intel                                                     |
| Architecture       | :Skylake                                                   |
| Model              | Family: 0x06, Model: 0x55, Stepping: 0x04, Type: 0x00      |
| Cores              | 10 physical cores, 20 logical cores (on executing CPU)     |
|                    | Hyperthreading detected                                    |
| Clock Frequencies  | 2200 / 3000 MHz (base/max), 100 MHz bus                    |
| Data Cache         | Level 1:3 : (32, 1024, 14080) kbytes                       |
|                    | 64 byte cache line size                                    |
| Address Size       | 48 bits virtual, 46 bits physical                          |
| SIMD               | 512 bit = 64 byte max. SIMD vector size                    |
| Time Stamp Counter | TSC is accessible via `rdtsc`                              |
|                    | TSC runs at constant rate (invariant from clock frequency) |
| Perf. Monitoring   | Performance Monitoring Counters (PMC) revision 4           |
|                    | Available hardware counters per logical core:              |
|                    | 3 fixed-function counters of 48 bit width                  |
|                    | 4 general-purpose counters of 48 bit width                 |
| Hypervisor         | No                                                         |

| Cpu Feature | Description                                                    |
|:----------- |:-------------------------------------------------------------- |
| ACPI        | Thermal monitor and software controlled clock facilities (MSR) |
| ADX         | Intel ADX (Multi-Precision Add-Carry Instruction Extensions)   |
| AES         | AES encryption instruction set                                 |
| AHF64       | LAHF and SAHF in PM64                                          |
| APIC        | APIC on-chip (Advanced Programmable Interrupt Controller)      |
| AVX         | 256bit Advanced Vector Extensions, AVX                         |
| AVX2        | SIMD 256bit Advanced Vector Extensions 2                       |
| AVX512BW    | AVX-512 Byte and Word Instructions                             |
| AVX512CD    | AVX-512 Conflict Detection Instructions                        |
| AVX512DQ    | AVX-512 Doubleword and Quadword Instructions                   |
| AVX512F     | AVX-512 Foundation                                             |
| AVX512VL    | AVX-512 Vector Length Extensions                               |
| BMI1        | Bit Manipulation Instruction Set 1                             |
| BMI2        | Bit Manipulation Instruction Set 2                             |
| CLFLUSH     | CLFLUSHOPT Instructions                                        |
| CLFSH       | CLFLUSH instruction (SSE2)                                     |
| CLWB        | CLWB instruction                                               |
| CMOV        | Conditional move CMOV and FCMOV instructions                   |
| CX16        | CMPXCHG16B instruction                                         |
| CX8         | CMPXCHG8 instruction (64bit compare and exchange)              |
| DCA         | Direct cache access for DMA writes                             |
| DE          | Debugging extensions                                           |
| DS          | Debug store to save trace of executed jumps                    |
| DSCPL       | CPL qualified debug store                                      |
| DTES64      | 64bit debug store                                              |
| ERMS        | Enhanced REP MOVSB/STOSB                                       |
| EST         | Enhanced SpeedStep                                             |
| F16C        | half-precision float support                                   |
| FMA3        | Fused multiply-add using three operands                        |
| FPDPR       | FPU CS and FPU DS deprecated                                   |
| FPU         | Onboard x87 FPU                                                |
| FSGS        | Access to base of %fs and %gs                                  |
| FXSR        | FXSAVE, FXRSTOR instructions                                   |
| HLE         | Transactional Synchronization Extensions                       |
| HTT         | Max APIC IDs reserved field is valid                           |
| INVPCID     | INVPCID instruction                                            |
| IPT         | Intel Processor Trace                                          |
| LM          | AMD64 long mode                                                |
| LZCNT       | LZCNT instruction                                              |
| MCA         | Machine Check Architecture (MSR)                               |
| MCE         | Machine check exception                                        |
| MMX         | 64bit Multimedia Streaming Extensions                          |
| MON         | MONITOR and MWAIT instructions                                 |
| MOVBE       | MOVBE instruction                                              |
| MPX         | Intel MPX (Memory Protection Extensions)                       |
| MSR         | Model Specific Registers, RDMSR and WRMSR instructions         |
| MTRR        | Memory Type Range Registers                                    |
| NX          | NXE                                                            |
| OSPKE       | PKU enabled by OS                                              |
| OSXSV       | XSAVE enabled by OS                                            |
| PAE         | Physical address extension                                     |
| PAT         | Page attribute table                                           |
| PBE         | Pending break enable wakeup support                            |
| PCID        | Process context identifiers                                    |
| PCLMUL      | PCLMULQDQ support                                              |
| PDCM        | Perfmon and debug capabilities                                 |
| PG1G        | PG1G                                                           |
| PGE         | Page global bit                                                |
| PKU         | Memory Protection Keys for User-mode pages                     |
| POPCNT      | POPCNT instruction                                             |
| PQE         | Platform Quality of Service Enforcement                        |
| PQM         | Platform Quality of Service Monitoring                         |
| PREFETCHW   | PREFETCHW instruction                                          |
| PSE         | Page size extensions                                           |
| PSE36       | 36bit page size extension                                      |
| RDRND       | On-chip random number generator                                |
| RDSEED      | RDSEED instruction                                             |
| RDTSCP      | RDTSCP instruction                                             |
| RTM         | Transactional Synchronization Extensions                       |
| SDBG        | Silicon debug interface                                        |
| SEP         | SYSENTER and SYSEXIT instructions                              |
| SMAP        | Supervisor Mode Access Prevention                              |
| SMEP        | Supervisor-Mode Execution Prevention                           |
| SMX         | Safer mode instructions                                        |
| SS          | Self Snoop                                                     |
| SSE         | 128bit Streaming SIMD Extensions 1                             |
| SSE2        | 128bit Streaming SIMD Extensions 2                             |
| SSE3        | 128bit Streaming SIMD Extensions 3                             |
| SSE41       | 128bit Streaming SIMD Extensions 4.1                           |
| SSE42       | 128bit Streaming SIMD Extensions 4.2                           |
| SSSE3       | 128bit Supplemental Streaming SIMD Extension 3                 |
| SYSCALL     | SYSCALL and SYSRET                                             |
| TM          | Thermal monitor with automatic thermal control                 |
| TM2         | Thermal monitor 2                                              |
| TSC         | Time stamp counter                                             |
| TSCADJ      | IA32_TSC_ADJUST                                                |
| TSCDL       | APIC one-shot operation using TSC deadline value               |
| TSCINV      | Invariant TSC                                                  |
| VME         | Virtual 8086 mode enhancements                                 |
| VMX         | Virtual machine extensions                                     |
| X2APIC      | x2APIC support                                                 |
| XSAVE       | XSAVE, XRESTOR, XSETBV, XGETBV                                 |
| XTPR        | disabling sending of task priority messages                    |



processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 85
model name	: Intel(R) Xeon(R) Silver 4114 CPU @ 2.20GHz
stepping	: 4
microcode	: 0x200005e
cpu MHz		: 2500.000
cache size	: 14080 KB
physical id	: 0
siblings	: 20
core id		: 0
cpu cores	: 10
apicid		: 0
initial apicid	: 0
fpu		: yes
fpu_exception	: yes
cpuid level	: 22
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cdp_l3 invpcid_single pti intel_ppin ssbd mba ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm mpx rdt_a avx512f avx512dq rdseed adx smap clflushopt clwb intel_pt avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req pku ospke md_clear flush_l1d
bugs		: cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass l1tf mds swapgs
bogomips	: 4400.00
clflush size	: 64
cache_alignment	: 64
address sizes	: 46 bits physical, 48 bits virtual
power management:
Test Summary: | Pass  Total
ReturnTypes   |   49     49
Dump of all cpuid leafs, used for mocking 'cpuid'...

# Intel(R) Xeon(R) Silver 4114 CPU @ 2.20GHz without hypervisor
push!( _mockdb, (Dict(
    ((0x00000000, 0x00000000) => (0x00000016, 0x756e6547, 0x6c65746e, 0x49656e69)),
    ((0x00000001, 0x00000000) => (0x00050654, 0x09200800, 0x7ffefbff, 0xbfebfbff)),
    ((0x00000002, 0x00000000) => (0x76036301, 0x00f0b5ff, 0x00000000, 0x00c30000)),
    ((0x00000003, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000004, 0x00000000) => (0x3c004121, 0x01c0003f, 0x0000003f, 0x00000000)),
    ((0x00000005, 0x00000000) => (0x00000040, 0x00000040, 0x00000003, 0x00002020)),
    ((0x00000006, 0x00000000) => (0x00000ef7, 0x00000002, 0x00000009, 0x00000000)),
    ((0x00000007, 0x00000000) => (0x00000000, 0xd39ffffb, 0x00000018, 0x9c002400)),
    ((0x00000008, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000009, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x0000000a, 0x00000000) => (0x07300404, 0x00000000, 0x00000000, 0x00000603)),
    ((0x0000000b, 0x00000000) => (0x00000001, 0x00000002, 0x00000100, 0x00000009)),
    ((0x0000000c, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x0000000d, 0x00000000) => (0x000002ff, 0x00000a88, 0x00000a88, 0x00000000)),
    ((0x0000000e, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x0000000f, 0x00000000) => (0x00000000, 0x0000004f, 0x00000000, 0x00000002)),
    ((0x00000010, 0x00000000) => (0x00000000, 0x0000000a, 0x00000000, 0x00000000)),
    ((0x00000011, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000012, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000013, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000014, 0x00000000) => (0x00000001, 0x0000000f, 0x00000007, 0x00000000)),
    ((0x00000015, 0x00000000) => (0x00000002, 0x000000b0, 0x00000000, 0x00000000)),
    ((0x00000016, 0x00000000) => (0x00000898, 0x00000bb8, 0x00000064, 0x00000000)),
    ((0x80000000, 0x00000000) => (0x80000008, 0x00000000, 0x00000000, 0x00000000)),
    ((0x80000001, 0x00000000) => (0x00000000, 0x00000000, 0x00000121, 0x2c100800)),
    ((0x80000002, 0x00000000) => (0x65746e49, 0x2952286c, 0x6f655820, 0x2952286e)),
    ((0x80000003, 0x00000000) => (0x6c695320, 0x20726576, 0x34313134, 0x55504320)),
    ((0x80000004, 0x00000000) => (0x32204020, 0x4730322e, 0x00007a48, 0x00000000)),
    ((0x80000005, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x80000006, 0x00000000) => (0x00000000, 0x00000000, 0x01006040, 0x00000000)),
    ((0x80000007, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000100)),
    ((0x80000008, 0x00000000) => (0x0000302e, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000004, 0x00000001) => (0x3c004122, 0x01c0003f, 0x0000003f, 0x00000000)),
    ((0x00000004, 0x00000002) => (0x3c004143, 0x03c0003f, 0x000003ff, 0x00000000)),
    ((0x00000004, 0x00000003) => (0x3c07c163, 0x0280003f, 0x00004fff, 0x00000004)),
    ((0x00000004, 0x00000004) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x0000000b, 0x00000001) => (0x00000005, 0x00000014, 0x00000201, 0x00000009)),
    ((0x0000000b, 0x00000002) => (0x00000000, 0x00000000, 0x00000002, 0x00000009)),
  ) => Dict{Symbol,Any}(
    :cpuvendor       => :Intel,
    :cpuarchitecture => :Skylake,
    :cpucores        => 10,
    :cputhreads      => 20,
    :cachesize       => (32768, 1048576, 14417920),
    :cachelinesize   => 64,
    :simdbits        => 512,
  )))

Done.



-----
Mocking CpuId
-----

Tested recorded cpuid table #1 for ''
Tested recorded cpuid table #2 for 'Intel(R) Xeon(R) CPU E5-2670 0 @ 2.60GHz'
Tested recorded cpuid table #3 for 'Intel(R) Xeon(R) CPU E5-2680 v2 @ 2.80GHz'
Tested recorded cpuid table #4 for 'Intel(R) Xeon(R) CPU E5-2680 v3 @ 2.50GHz'
Tested recorded cpuid table #5 for 'Intel(R) Xeon(R) CPU E5-2670 0 @ 2.60GHz'
Tested recorded cpuid table #6 for 'Intel(R) Xeon(R) CPU           X5570  @ 2.93GHz'
Tested recorded cpuid table #7 for 'Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz'
Tested recorded cpuid table #8 for 'Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz'
Tested recorded cpuid table #9 for 'Intel(R) Xeon Phi(TM) CPU 7250 @ 1.40GHz'
Tested recorded cpuid table #10 for 'Intel(R) Xeon(R) CPU E3-1241 v3 @ 3.50GHz'
Tested recorded cpuid table #11 for 'Intel(R) Core(TM) i7-6600U CPU @ 2.60GHz'
Tested recorded cpuid table #12 for 'AMD A10-8700P Radeon R6, 10 Compute Cores 4C+6G'
Tested recorded cpuid table #13 for 'AMD Ryzen Threadripper 1950X 16-Core Processor'
Tested recorded cpuid table #14 for 'AMD A8-6410 APU with AMD Radeon R5 Graphics'
Tested recorded cpuid table #15 for 'AMD Athlon(tm) 5350 APU with Radeon(tm) R3'
Tested recorded cpuid table #16 for 'AMD EPYC 7401P 24-Core Processor'
Test Summary: | Pass  Broken  Total
Mocking       |  174       2    176
   Testing CpuId tests passed 

Results with Julia v1.3.1-pre-7704df0a5a

Testing was successful. Last evaluation was ago and took 1 minute, 9 seconds.

Click here to download the log file.

 Resolving package versions...
 Installed CpuId ─ v0.2.2
  Updating `~/.julia/environments/v1.3/Project.toml`
  [adafc99b] + CpuId v0.2.2
  Updating `~/.julia/environments/v1.3/Manifest.toml`
  [adafc99b] + CpuId v0.2.2
  [2a0f44e3] + Base64 
  [8ba89e20] + Distributed 
  [b77e0a4c] + InteractiveUtils 
  [56ddb016] + Logging 
  [d6f4376e] + Markdown 
  [9a3f8284] + Random 
  [9e88b42a] + Serialization 
  [6462fe0b] + Sockets 
  [8dfed614] + Test 
   Testing CpuId
    Status `/tmp/jl_lQHJho/Manifest.toml`
  [adafc99b] CpuId v0.2.2
  [2a0f44e3] Base64  [`@stdlib/Base64`]
  [8ba89e20] Distributed  [`@stdlib/Distributed`]
  [b77e0a4c] InteractiveUtils  [`@stdlib/InteractiveUtils`]
  [56ddb016] Logging  [`@stdlib/Logging`]
  [d6f4376e] Markdown  [`@stdlib/Markdown`]
  [9a3f8284] Random  [`@stdlib/Random`]
  [9e88b42a] Serialization  [`@stdlib/Serialization`]
  [6462fe0b] Sockets  [`@stdlib/Sockets`]
  [8dfed614] Test  [`@stdlib/Test`]
| Cpu Property       | Value                                                      |
|:------------------ |:---------------------------------------------------------- |
| Brand              | Intel(R) Xeon(R) Silver 4114 CPU @ 2.20GHz                 |
| Vendor             | :Intel                                                     |
| Architecture       | :Skylake                                                   |
| Model              | Family: 0x06, Model: 0x55, Stepping: 0x04, Type: 0x00      |
| Cores              | 10 physical cores, 20 logical cores (on executing CPU)     |
|                    | Hyperthreading detected                                    |
| Clock Frequencies  | 2200 / 3000 MHz (base/max), 100 MHz bus                    |
| Data Cache         | Level 1:3 : (32, 1024, 14080) kbytes                       |
|                    | 64 byte cache line size                                    |
| Address Size       | 48 bits virtual, 46 bits physical                          |
| SIMD               | 512 bit = 64 byte max. SIMD vector size                    |
| Time Stamp Counter | TSC is accessible via `rdtsc`                              |
|                    | TSC runs at constant rate (invariant from clock frequency) |
| Perf. Monitoring   | Performance Monitoring Counters (PMC) revision 4           |
|                    | Available hardware counters per logical core:              |
|                    | 3 fixed-function counters of 48 bit width                  |
|                    | 4 general-purpose counters of 48 bit width                 |
| Hypervisor         | No                                                         |

| Cpu Feature | Description                                                    |
|:----------- |:-------------------------------------------------------------- |
| ACPI        | Thermal monitor and software controlled clock facilities (MSR) |
| ADX         | Intel ADX (Multi-Precision Add-Carry Instruction Extensions)   |
| AES         | AES encryption instruction set                                 |
| AHF64       | LAHF and SAHF in PM64                                          |
| APIC        | APIC on-chip (Advanced Programmable Interrupt Controller)      |
| AVX         | 256bit Advanced Vector Extensions, AVX                         |
| AVX2        | SIMD 256bit Advanced Vector Extensions 2                       |
| AVX512BW    | AVX-512 Byte and Word Instructions                             |
| AVX512CD    | AVX-512 Conflict Detection Instructions                        |
| AVX512DQ    | AVX-512 Doubleword and Quadword Instructions                   |
| AVX512F     | AVX-512 Foundation                                             |
| AVX512VL    | AVX-512 Vector Length Extensions                               |
| BMI1        | Bit Manipulation Instruction Set 1                             |
| BMI2        | Bit Manipulation Instruction Set 2                             |
| CLFLUSH     | CLFLUSHOPT Instructions                                        |
| CLFSH       | CLFLUSH instruction (SSE2)                                     |
| CLWB        | CLWB instruction                                               |
| CMOV        | Conditional move CMOV and FCMOV instructions                   |
| CX16        | CMPXCHG16B instruction                                         |
| CX8         | CMPXCHG8 instruction (64bit compare and exchange)              |
| DCA         | Direct cache access for DMA writes                             |
| DE          | Debugging extensions                                           |
| DS          | Debug store to save trace of executed jumps                    |
| DSCPL       | CPL qualified debug store                                      |
| DTES64      | 64bit debug store                                              |
| ERMS        | Enhanced REP MOVSB/STOSB                                       |
| EST         | Enhanced SpeedStep                                             |
| F16C        | half-precision float support                                   |
| FMA3        | Fused multiply-add using three operands                        |
| FPDPR       | FPU CS and FPU DS deprecated                                   |
| FPU         | Onboard x87 FPU                                                |
| FSGS        | Access to base of %fs and %gs                                  |
| FXSR        | FXSAVE, FXRSTOR instructions                                   |
| HLE         | Transactional Synchronization Extensions                       |
| HTT         | Max APIC IDs reserved field is valid                           |
| INVPCID     | INVPCID instruction                                            |
| IPT         | Intel Processor Trace                                          |
| LM          | AMD64 long mode                                                |
| LZCNT       | LZCNT instruction                                              |
| MCA         | Machine Check Architecture (MSR)                               |
| MCE         | Machine check exception                                        |
| MMX         | 64bit Multimedia Streaming Extensions                          |
| MON         | MONITOR and MWAIT instructions                                 |
| MOVBE       | MOVBE instruction                                              |
| MPX         | Intel MPX (Memory Protection Extensions)                       |
| MSR         | Model Specific Registers, RDMSR and WRMSR instructions         |
| MTRR        | Memory Type Range Registers                                    |
| NX          | NXE                                                            |
| OSPKE       | PKU enabled by OS                                              |
| OSXSV       | XSAVE enabled by OS                                            |
| PAE         | Physical address extension                                     |
| PAT         | Page attribute table                                           |
| PBE         | Pending break enable wakeup support                            |
| PCID        | Process context identifiers                                    |
| PCLMUL      | PCLMULQDQ support                                              |
| PDCM        | Perfmon and debug capabilities                                 |
| PG1G        | PG1G                                                           |
| PGE         | Page global bit                                                |
| PKU         | Memory Protection Keys for User-mode pages                     |
| POPCNT      | POPCNT instruction                                             |
| PQE         | Platform Quality of Service Enforcement                        |
| PQM         | Platform Quality of Service Monitoring                         |
| PREFETCHW   | PREFETCHW instruction                                          |
| PSE         | Page size extensions                                           |
| PSE36       | 36bit page size extension                                      |
| RDRND       | On-chip random number generator                                |
| RDSEED      | RDSEED instruction                                             |
| RDTSCP      | RDTSCP instruction                                             |
| RTM         | Transactional Synchronization Extensions                       |
| SDBG        | Silicon debug interface                                        |
| SEP         | SYSENTER and SYSEXIT instructions                              |
| SMAP        | Supervisor Mode Access Prevention                              |
| SMEP        | Supervisor-Mode Execution Prevention                           |
| SMX         | Safer mode instructions                                        |
| SS          | Self Snoop                                                     |
| SSE         | 128bit Streaming SIMD Extensions 1                             |
| SSE2        | 128bit Streaming SIMD Extensions 2                             |
| SSE3        | 128bit Streaming SIMD Extensions 3                             |
| SSE41       | 128bit Streaming SIMD Extensions 4.1                           |
| SSE42       | 128bit Streaming SIMD Extensions 4.2                           |
| SSSE3       | 128bit Supplemental Streaming SIMD Extension 3                 |
| SYSCALL     | SYSCALL and SYSRET                                             |
| TM          | Thermal monitor with automatic thermal control                 |
| TM2         | Thermal monitor 2                                              |
| TSC         | Time stamp counter                                             |
| TSCADJ      | IA32_TSC_ADJUST                                                |
| TSCDL       | APIC one-shot operation using TSC deadline value               |
| TSCINV      | Invariant TSC                                                  |
| VME         | Virtual 8086 mode enhancements                                 |
| VMX         | Virtual machine extensions                                     |
| X2APIC      | x2APIC support                                                 |
| XSAVE       | XSAVE, XRESTOR, XSETBV, XGETBV                                 |
| XTPR        | disabling sending of task priority messages                    |



processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 85
model name	: Intel(R) Xeon(R) Silver 4114 CPU @ 2.20GHz
stepping	: 4
microcode	: 0x200005e
cpu MHz		: 2499.999
cache size	: 14080 KB
physical id	: 0
siblings	: 20
core id		: 0
cpu cores	: 10
apicid		: 0
initial apicid	: 0
fpu		: yes
fpu_exception	: yes
cpuid level	: 22
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cdp_l3 invpcid_single pti intel_ppin ssbd mba ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm mpx rdt_a avx512f avx512dq rdseed adx smap clflushopt clwb intel_pt avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req pku ospke md_clear flush_l1d
bugs		: cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass l1tf mds swapgs
bogomips	: 4400.00
clflush size	: 64
cache_alignment	: 64
address sizes	: 46 bits physical, 48 bits virtual
power management:
Test Summary: | Pass  Total
ReturnTypes   |   49     49
Dump of all cpuid leafs, used for mocking 'cpuid'...

# Intel(R) Xeon(R) Silver 4114 CPU @ 2.20GHz without hypervisor
push!( _mockdb, (Dict(
    ((0x00000000, 0x00000000) => (0x00000016, 0x756e6547, 0x6c65746e, 0x49656e69)),
    ((0x00000001, 0x00000000) => (0x00050654, 0x35200800, 0x7ffefbff, 0xbfebfbff)),
    ((0x00000002, 0x00000000) => (0x76036301, 0x00f0b5ff, 0x00000000, 0x00c30000)),
    ((0x00000003, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000004, 0x00000000) => (0x3c004121, 0x01c0003f, 0x0000003f, 0x00000000)),
    ((0x00000005, 0x00000000) => (0x00000040, 0x00000040, 0x00000003, 0x00002020)),
    ((0x00000006, 0x00000000) => (0x00000ef7, 0x00000002, 0x00000009, 0x00000000)),
    ((0x00000007, 0x00000000) => (0x00000000, 0xd39ffffb, 0x00000018, 0x9c002400)),
    ((0x00000008, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000009, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x0000000a, 0x00000000) => (0x07300404, 0x00000000, 0x00000000, 0x00000603)),
    ((0x0000000b, 0x00000000) => (0x00000001, 0x00000002, 0x00000100, 0x00000035)),
    ((0x0000000c, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x0000000d, 0x00000000) => (0x000002ff, 0x00000a88, 0x00000a88, 0x00000000)),
    ((0x0000000e, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x0000000f, 0x00000000) => (0x00000000, 0x0000004f, 0x00000000, 0x00000002)),
    ((0x00000010, 0x00000000) => (0x00000000, 0x0000000a, 0x00000000, 0x00000000)),
    ((0x00000011, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000012, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000013, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000014, 0x00000000) => (0x00000001, 0x0000000f, 0x00000007, 0x00000000)),
    ((0x00000015, 0x00000000) => (0x00000002, 0x000000b0, 0x00000000, 0x00000000)),
    ((0x00000016, 0x00000000) => (0x00000898, 0x00000bb8, 0x00000064, 0x00000000)),
    ((0x80000000, 0x00000000) => (0x80000008, 0x00000000, 0x00000000, 0x00000000)),
    ((0x80000001, 0x00000000) => (0x00000000, 0x00000000, 0x00000121, 0x2c100800)),
    ((0x80000002, 0x00000000) => (0x65746e49, 0x2952286c, 0x6f655820, 0x2952286e)),
    ((0x80000003, 0x00000000) => (0x6c695320, 0x20726576, 0x34313134, 0x55504320)),
    ((0x80000004, 0x00000000) => (0x32204020, 0x4730322e, 0x00007a48, 0x00000000)),
    ((0x80000005, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x80000006, 0x00000000) => (0x00000000, 0x00000000, 0x01006040, 0x00000000)),
    ((0x80000007, 0x00000000) => (0x00000000, 0x00000000, 0x00000000, 0x00000100)),
    ((0x80000008, 0x00000000) => (0x0000302e, 0x00000000, 0x00000000, 0x00000000)),
    ((0x00000004, 0x00000001) => (0x3c004122, 0x01c0003f, 0x0000003f, 0x00000000)),
    ((0x00000004, 0x00000002) => (0x3c004143, 0x03c0003f, 0x000003ff, 0x00000000)),
    ((0x00000004, 0x00000003) => (0x3c07c163, 0x0280003f, 0x00004fff, 0x00000004)),
    ((0x00000004, 0x00000004) => (0x00000000, 0x00000000, 0x00000000, 0x00000000)),
    ((0x0000000b, 0x00000001) => (0x00000005, 0x00000014, 0x00000201, 0x00000035)),
    ((0x0000000b, 0x00000002) => (0x00000000, 0x00000000, 0x00000002, 0x00000035)),
  ) => Dict{Symbol,Any}(
    :cpuvendor       => :Intel,
    :cpuarchitecture => :Skylake,
    :cpucores        => 10,
    :cputhreads      => 20,
    :cachesize       => (32768, 1048576, 14417920),
    :cachelinesize   => 64,
    :simdbits        => 512,
  )))

Done.



-----
Mocking CpuId
-----

Tested recorded cpuid table #1 for ''
Tested recorded cpuid table #2 for 'Intel(R) Xeon(R) CPU E5-2670 0 @ 2.60GHz'
Tested recorded cpuid table #3 for 'Intel(R) Xeon(R) CPU E5-2680 v2 @ 2.80GHz'
Tested recorded cpuid table #4 for 'Intel(R) Xeon(R) CPU E5-2680 v3 @ 2.50GHz'
Tested recorded cpuid table #5 for 'Intel(R) Xeon(R) CPU E5-2670 0 @ 2.60GHz'
Tested recorded cpuid table #6 for 'Intel(R) Xeon(R) CPU           X5570  @ 2.93GHz'
Tested recorded cpuid table #7 for 'Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz'
Tested recorded cpuid table #8 for 'Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz'
Tested recorded cpuid table #9 for 'Intel(R) Xeon Phi(TM) CPU 7250 @ 1.40GHz'
Tested recorded cpuid table #10 for 'Intel(R) Xeon(R) CPU E3-1241 v3 @ 3.50GHz'
Tested recorded cpuid table #11 for 'Intel(R) Core(TM) i7-6600U CPU @ 2.60GHz'
Tested recorded cpuid table #12 for 'AMD A10-8700P Radeon R6, 10 Compute Cores 4C+6G'
Tested recorded cpuid table #13 for 'AMD Ryzen Threadripper 1950X 16-Core Processor'
Tested recorded cpuid table #14 for 'AMD A8-6410 APU with AMD Radeon R5 Graphics'
Tested recorded cpuid table #15 for 'AMD Athlon(tm) 5350 APU with Radeon(tm) R3'
Tested recorded cpuid table #16 for 'AMD EPYC 7401P 24-Core Processor'
Test Summary: | Pass  Broken  Total
Mocking       |  174       2    176
   Testing CpuId tests passed